Principal Digital Design Engineer

Principal Digital Design EngineerLocation: Ottawa, CanadaTime Type: Full timePosted on: Posted YesterdayAbout MarvellMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.Your Team, Your ImpactOptical PHY BU develops cutting-edge optical Ethernet Transceiver ASICs. Current online working and meetings that are through mediums such as Zoom and Webex are all based on cloud services. In order to respond to the dramatically increased demands of cloud-based connection capability, major cloud computing companies urgently demand faster and more secure internet connection components. One critical part of that component includes the optical ethernet transceiver ASICs. As a member of a digital hardware development team, the candidate will be assisting in chip design, verification, supporting back-end teams and timing closure.What You Can ExpectHigh speed data path RTL implementation using Verilog, synthesis and backend resources.Integrate vendor IP and support.Well versed with the complete ASIC flow from micro-architecture to customer deployment.Post-silicon debug and correlation.Specify and implement digital features of a chip.Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification.Develop ASIC specification and micro-architecture of signal processing and communications algorithms.Assist in design automation of various aspects of the CAD EDA flow.Mentorship of junior team members.What We're Looking ForBachelors, Masters or PhD with minimum 8+ years of experience (or equivalent) in multi-million gates digital/mixed-signal IC design at 16nm or smaller technology.Experience of entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.Strong language user in Verilog, System Verilog, Perl, Unix Shell.Experience in both RTL development (block and subsystem level) and gate level verification and debug.Hands on experience with matching DSP block model functionality to RTL's, synthesis, static timing analysis and functional verification.Strong design experience in high speed DSP physical layer products.Experience with chip bring up and functional validation of the product in the lab.Strong system level modeling, debugging and troubleshooting.Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment.Effective communication and presentation skills.Team player.Additional Compensation and Benefit ElementsWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #J-18808-Ljbffr