Experienced Physical Design Engineer

Unlock Your Potential as a Ground-Breaking Physical Design Engineer

At Apple Inc., we're dedicated to crafting innovative products that transform lives. If you're passionate about tackling complex challenges and pushing the boundaries of what's possible, we invite you to join our team of visionary engineers.

About the Role

We're seeking a highly skilled Physical Design Engineer to join our Munich-based team. As a key member of our multidisciplinary group, you'll have the rare opportunity to contribute to the development of cutting-edge products that will captivate millions of Apple's customers worldwide.

Key Responsibilities

1. Develop and implement static timing analysis for high-speed IP's, including analog mixed-signal interfaces.
2. Configure and optimize CTS settings for high-frequency, multi-clock networks.
3. Create floor-plans under strict area constraints, ensuring seamless integration with full-chip designs.
4. Optimize power consumption throughout the implementation process.
5. Perform full place and route flow on hierarchical design blocks, meeting stringent timing, area, and power targets.
6. Implement functional, timing, noise, and EMIR ECO's.
7. Conduct physical design verification, providing feedback to hard macro owners and other teams.
8. Participate in physical design methodologies meetings.
9. Contribute to the development of our advanced AMS flow, further enhancing our industry-leading environment.

Requirements

• Proven expertise in floor-planning, place and route, physical verification, timing closure, and power/functional verification.
• Fluent English language skills, both written and spoken.

Preferred Qualifications

• Bachelor's degree in Electrical Engineering.
• Experience with high-PHY and/or SOC designs.
• Knowledge of low-power implementation for static and dynamic scenarios, as well as UPF power intent flow.
• Deep understanding of timing constraints, timing exceptions, clock setup, and timing debugging.
• Proficiency in Basic SoC Architecture and HDL languages like Verilog.
• Advanced skills in industry-standard Physical Design, Static Timing Analysis, and Synthesis tools.
• Deep understanding of scripting languages such as Perl/Tcl/shell.
• Hands-on experience with functional ECO implementation and equivalence checking and debugging.
• Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.